Integrated CMOS logic circuits exist in two basic varieties: static and dynamic CMOS field-effect transistor ("FET") logic gates. Both varieties have at least one input and at least one output. A static CMOS logic gate typically requires no external clock signal to control its operation. Moreover, the static CMOS logic gate can preserve its state for as long as the power supply is applied to it. A dynamic CMOS logic gate, on the other hand, typically does not hold its state indefinitely and requires an external clock signal for its operation, which external clock defines alternating periods of precharging and evaluating the logic gate.
Dynamic CMOS logic gates tend to yield better performance, consume less power, and require less silicon area to be fabricated than static CMOS logic gates. Therefore, various dynamic circuits have been proposed, and FIGS. 1a, 1b and 1c illustrate various prior dynamic CMOS logic gates.
In FIG. 1a, a dynamic CMOS logic gate 9 comprises an NFET logic network 13, a precharge transistor 11, and an evaluate transistor 12. For illustration purposes NFET logic network 13 includes only NFETs (N-channel field effect transistors) 13a and 13b for performing a predefined logic function with respect to their inputs InA and InB. The particular N-logic gate shown in FIG. 1a provides a NAND function for the dynamic CMOS gate 9; it will be appreciated that other logic functions may be implemented, including standard (e.g. NOR, etc.) and random logic gates. Transistor 11 is a PFET (P-channel field effect transistor), and transistor 12 is an NFET (N channel field effect transistor). It will be appreciated that dynamic CMOS logic gates may also be implemented with a PFET logic (P-logic) network or with alternating NFET logic networks (N-logic) and PFET logic networks (as in the case of dynamic NORA). The state of dynamic CMOS logic gate 9 is stored on the parasitic capacitance of its output node, shown in phantom (dashed lines) as parasitic capacitor 14 coupled between output node 15 and ground or V.sub.SS or a predetermined reference voltage. A clock signal CLK is applied to the gate of transistors 11 and 12 to control the operation of gate 9.
As is well known in the art, the clock signal of a dynamic CMOS gate such as the gate 9 of FIG. 1a typically includes two phases (or periods) known as precharge and evaluate phases. The clock signal CLK is coupled to the gates of the precharge and evaluate transistors to control the precharge and evaluate phases, and the clock alternates between these phases. The clock waveform 701 of FIG. 7b shows that the clock signal has alternating phases which include the precharge phase when the clock is low (shown as 703) and the evaluate phase when the clock is high (shown as 702). During the operation of the dynamic CMOS logic gate 9, the output (at node 15) of logic gate 9 is first precharged. The clock signal CLK is, during the precharge phase, at a logical low voltage state (shown as ground, which is one of several possible reference voltage states) that turns on transistor 11 to precharge the output node 15 of the gate 9. The clock signal CLK then, during the evaluate phase, changes its state to thereby turn off precharge transistor 11 and switch on evaluate transistor 12 to allow logic network 13 to perform its logic function with respect to its inputs InA and InB. Evaluation of the logic state of the logic network is only performed when the clock signal CLK is at logical high in the case of an N-logic network such as logic network 13. When the inputs of logic network 13 cause output node 15 to connect to ground, the electrical charge stored in the output node 15 is discharged through logic network 13 and transistor 12, and dynamic circuit 9 outputs a logical low signal. This action is referred to as conditional discharge since it occurs only when the logic function driven by inputs InA and InB specifies a logical low output. When the inputs of network 13 cause output node 15 not to connect to ground, output node 15 holds its electrical charge (provided by the precharge phase) and dynamic circuit outputs a logical high signal as precharged by precharge transistor 11.
It will be appreciated that when a P-logic network is used in a CMOS dynamic logic gate, the precharge phase causes a discharge of the output node through an NFET (e.g. a pull-down to ground of the output node) and the p-logic network conditionally pulls up the discharged output node during the evaluate phase of the logic gate. P-logic networks are often used in alternating fashion with N-logic networks in NORA CMOS dynamic logic; see, for example pages 233-236 of CMOS Digital Circuit Technology, M. Shoji, Prentice Hall, 1988; and pages 171-172 of Principles of CMOS VLSI Design-A Systems Perspective, N. H. E. Weste and K. Eshraghian, Addison-Wesley Publishing Co., 1985.
FIGS. 1b and 1c illustrate alternative dynamic CMOS logic gates which are known in the prior art (again, N-logic networks are used in both cases, but P-logic networks may also be used according to the well known rules applicable to these logic networks). FIG. 1b shows a dynamic CMOS logic gate 9a where the evaluate transistor has been eliminated to achieve higher speed operation for the logic gate. The logic network 16 (containing for illustration purposes NFETs 16a and 16b to provide a NAND function for the logic gate) during the evaluate phase conditionally pulls-down the precharged output node 15a, which node was precharged by the precharge PFET 11a during the precharge phase of the clock signal. The clock signal "CLK" is coupled to the gate of the precharge PFET 11a to precharge the output node 15a to approximately a reference voltage, such as V.sub.DD during the precharge phase; typically the precharge occurs when the clock signal is a logical low which turns on the PFET 11a causing it to pull up the node 15a to approximately V.sub.DD. During the evaluate phase, the clock signal is a logical high which turns off the PFET 11a, thereby allowing the N-logic network 16 to conditionally discharge the output node 15a.
FIG. 1c illustrates another prior art dynamic CMOS logic gate 17 wherein a node or nodes within the logic network ("internal nodes") are precharged as well as the output node. Again, a P-logic network may be used in place of the N-logic network 19 shown in FIG. 1c provided the well known rules applicable to these networks are followed. Precharging of internal nodes in the logic network is a useful technique when charge sharing is to be minimized. Charge sharing is a known problem with several prior art dynamic CMOS logic gates, and occurs whenever the output node of a logic gate shares charge with an intermediate (an internal node) along a series pull down (or pull up) path in the logic network. The precharging of internal nodes prevents charge sharing as the internal nodes are charged to the same level as the output node and thus will not tend to dissipate charge from the output node. The logic gate 17 operates in the same fashion as logic gate 9 of FIG. 1a except that PFET 18 charges the internal node 15b during the precharge phase of the clock signal while the PFET 11 charges the output node 15. During the evaluate phase of the clock, both PFETs 11 and 18 are completely off while the evaluate NEFT 12 is turned on to allow the logic network 19 to conditionally discharge the output node 15.
The different varieties of dynamic CMOS logic gates, such as those shown in FIGS. 1a, 1b and 1c, may be illustrated in a generic form because these different gates share common features such as at least one input and at least one output and a clock input for controlling the precharge and evaluate phases of the logic gate. FIG. 1d shows a generic form of a dynamic CMOS logic gate, and this generic form represents the different varieties, including those gates shown in FIGS. 1a, 1b and 1c. It will be understood that this generic gate 10 is coupled to two commonly used reference voltages (e.g. V.sub.DD and V.sub.SS), even though not shown. This generic gate 10 may also represent a dynamic CMOS logic gate where a PFET logic network is used, although in this case, the clock signal used for this PFET network will be the complement of signal "CLK" (referred to as "clock bar" or CLK or "CLK-BAR"). This generic gate 10 will be used throughout this description in order to demonstrate that the invention may be used in many different types of dynamic CMOS logic gates.
As noted above, dynamic CMOS logic yields better performance in terms of speed and requires less silicon area to be fabricated than static CMOS logic. Nevertheless, for many CMOS integrated circuits (IC's), static CMOS logic is used because the IC is used in a portable device (e.g. a laptop computer) which must be powered by batteries; in this circumstance, as is well known, it is often necessary to conserve battery power by turning off or slowing down the system clocks of the portable device. Thus, in this circumstance, a chip designer faced with the trade off of (a) faster and denser dynamic CMOS logic versus (b) more conventional, larger, slower static CMOS logic, will select the static CMOS logic. However, the design of higher performance processors is now often requiring dynamic CMOS logic because of the performance advantages of dynamic CMOS logic. Thus, there exists a need to make dynamic CMOS logic operate statically in order to allow the system clocks to be stopped completely or to be run very slowly.
It will be appreciated that in conventional dynamic CMOS logic, such as the logic gates of FIGS. 1a, 1b and 1c, the clock cannot be stopped (or even run too slowly) because of the charge leakage off the output node of the gate. That is, when the precharging transistor is turned off for an extended period of time (e.g. because the clock has stopped in the evaluate phase or is running very slowly), then the charge on the precharged output node tends to leak off causing logic errors when the node should still be charged.
One prior approach to solving the problem of making a dynamic CMOS logic gate operate statically is shown in FIG. 2a and is also described on pages 168-169 of Weste and Eshraghian. As can be seen from FIG. 2a, an additional P-.channel transistor 20 is coupled to the output node of the dynamic CMOS logic gate 10. Transistor 20 is a weak P-channel transistor which is coupled between the reference voltage (e.g. power supply) V.sub.DD and the output node of gate 10. Transistor 20 is always on, which provides a constant hold current to the output node during evaluation of the gate. This hold current typically overwhelms the leakage current, therefore preserving the state of the gate during evaluation and making the gate less sensitive to noise. This approach allows the logic gate 10 to be operated statically by turning off the clock (e.g. keeping the clock held high) or to be operated with a very slow clock.
This prior art approach has numerous disadvantages. One disadvantage is that the prior dynamic gate of FIG. 2a consumes relatively more power than the logic gate 10 itself. This is due to the fact that transistor 20 is maintained constantly on. The constant on transistor 20 typically causes the prior dynamic gate of FIG. 2a to dissipate more power during the evaluation phase.
Another disadvantage is that the prior approach of FIG. 2a results in the use of the extra transistor in the prior dynamic CMOS gate (i.e., transistor 20). It will be appreciated that PFET 20 is in addition to the precharge PFET 11. The extra transistor typically causes the prior dynamic gate of FIG. 2a to occupy more space on the semiconductor (e.g. silicon) substrate, which also tends to increase the cost of this prior dynamic CMOS gate. Moreover, because transistor 20 is a weak transistor, the channel of the transistor needs to be made extra long in order to make the transistor weak (Weste and Eshraghian note that the PFET 20's width/length ratio must be small, requiring that the channel length be made long). This typically causes transistor 20 to occupy more area on the semiconductor substrate. Furthermore, PFET 20 may impact the speed performance of the logic gate of FIG. 2a.
In addition to not being able to operate well statically, dynamic CMOS logic also tends to suffer from a lack of immunity to noise (e.g. from input glitches) and from a problem known as charge sharing, which was described above. The precharged output nodes tend to be very sensitive to noise, and it is clear that once a glitch causes an output node to discharge (or to "bleed off" some of the charge) during an evaluation phase, the node will erroneously remain discharged (or partially discharged) during that evaluation phase, thereby causing logic errors. This is unlike static CMOS where the constantly powered pull-up or pull-down devices tend to correct for the noise. Therefore, there is a need to provide better noise immunity and freedom from charge sharing in dynamic CMOS logic, and some solutions to these problems have been provided in the prior art. The static gate 10 of FIG. 2a is resistant to noise (e.g. glitch resistant) and thus tends to be "glitch robust" meaning that the gate is more tolerant of glitches.
FIG. 2b illustrates a prior approach which employs an extra transistor 23 with a bias voltage applied to the gate of transistor 23 in order to improve noise immunity. The approach of FIG. 2b also is glitch robust. The bias voltage biases the transistor 23 to generate a constant hold current, which typically ranges between 0.2 to 1 microampere (.mu.A). This prior approach at improving noise immunity is described at pages 96-98 and shown at FIG. 3.78(b) of Introduction to nMOS and CMOS VLSI Systems Design, Amar Mukherjee, Prentice-Hall, 1986. The constant hold current provides for noise immunity by keeping the output node from erroneously discharging as a result of an input glitch. The constant hold current also tends to keep the output node at its precharged state (by supplying charge to the output node) even when charge sharing occurs when an internal node dissipates charge from the output node. Mukjerjee notes that when transistor 23 is a P-channel device (as shown in FIG. 2b), the bias voltage applied to the gate of the device is between V.sub.DD and V.sub.SS. Note that transistor 23 is in addition to the precharge transistor of the dynamic CMOS logic gate 10. It appears that the bias voltage applied to the gate of the transistor 23 is above the threshold voltage of transistor 23.
One disadvantage of the prior approach of FIG. 2b is the use of the extra transistor 23 in each logic gate. The extra transistor typically causes this prior dynamic gate to occupy more space on the silicon substrate, as described above. Furthermore, the wiring needed to distribute a separate bias voltage to each logic gate of this type on a chip also causes this gate to occupy more area.
FIG. 2c illustrates another prior approach which attaches a weak P-channel transistor 21 with a feedback inverter 22 to the output node of the dynamic CMOS logic gate 10. The approach of FIG. 2c is not as "glitch robust" as the approaches of FIGS. 2a and 2b. Transistor 21 is controlled by a feedback signal from inverter 22 to provide a small hold current, making the output node of dynamic CMOS logic gate 10 less sensitive to noise but still not as glitch resistant as the circuits shown in FIGS. 2a or 2b. With the arrangement shown in FIG. 2c, transistor 21 is turned on only when the precharged state is to be preserved. This prior approach of FIG. 2c is also described at pages 168-169 of Weste and Eshraghian.
One disadvantage of this prior approach of FIG. 2c is the use of weak transistor 21 in the circuit. This prior approach uses an extra transistor in addition to the logic gate 10, which typically causes the prior dynamic gate of FIG. 2b to occupy more silicon space on the substrate during fabrication. As described above, a weak transistor typically occupies more space to manufacture. Thus not only is an extra transistor required for each logic gate, it is an extra large transistor. Moreover, an inverter (often a PFET and NFET) is also required for each logic gate thereby further increasing the size of each logic gate. In addition, the weak transistor must be adequately weak to be quickly and easily overcome by the pull down operation of the logic network during evaluation. Additional power is also consumed when the pull down by the logic network occurs because the pull down operation must overcome the current from PFET 21.
FIGS. 3a through 3c illustrate another prior approach to solving the problems of lack of noise immunity and charge sharing; this approach is described in an article entitled ZIPPER CMOS by C. M. Lee and E. W. Szeto, IEEE Circuits and Devices Magazine, pp. 10-16, May 1986. A basic prior Zipper CMOS structure typically includes a zipper clock driver circuit 31 and alternating N-logic and P-logic networks. FIGS. 3a-3c show only the N logic gate 30 and its associated zipper clock driver 31 of the zipper CMOS structure, for illustration purposes only. As can be seen from FIGS. 3a and 3b, zipper clock driver 31 applies a clock signal referred to as ST' to a precharge transistor 35 of the dynamic CMOS gate 30 (via line 33) and a clock signal ST, to an evaluate transistor 36 of the dynamic CMOS gate 30. The clock signal ST is the standard rail to rail clock used for prior dynamic CMOS gate, such as gate 9 of FIG. 1a; clock waveform 701 of FIG. 7b shows an example of this standard clock signal. Zipper logic requires that two separate clock signals be distributed to all N-logic gates and two more separate clock signals be distributed to all P-logic gates. This doubling of the number of globally distributed clock signals causes the zipper logic gates to occupy more semiconductor area than other logic gates and the extra clocks consume additional power relative to dynamic logic gates which use fewer clocks. Zipper logic is shown by Lee and Szeto to have two alternative clock driver circuits (known as type 1 and type 2 zipper driver circuits).
In the zipper CMOS approach, the voltage level of the CLK clock signal is-modified by zipper clock driver 31 to provide the ST' signal such that precharge transistor 35 will stay slightly on during the evaluation phase. FIG. 3c illustrates both types of circuits of zipper clock driver 31 of FIG. 3a for N-logic gates in zipper logic. FIG. 4 illustrates the waveform of the ST' clock signal (curve 48), the ST signal (curve 47), and the CLK signal 406 (curve 49), which is the input to the zipper clock driver 31.
FIG. 3c shows a circuit diagram of a clock driver designed for use with N-logic gates in zipper logic, including both type 1 and type 2 alternatives and a generalized diode type 414. Normally, the zipper clock driver 31 has either PFET 416 (for the type 1 zipper driver) or NFET 418 (for the type 2 zipper driver) but not both. Diode 414 is not actually part of the circuit; it is shown merely to illustrate conceptually that PFET 416 or NFET 418 acts as a diode in the clock driver 31. The zipper clock driver 31 receives the CLK signal 406 as an input and produces two output clock signals ST 402 and ST' 404 to control N-channel evaluate transistors and P-channel precharge transistors respectively. When the input signal 406 is high, both outputs 402 and 404 are low, and when the input signal 406 is low, output ST 402 is high (e.g. V.sub.DD) and output ST' 404 is driven below, by an offset, the high state of ST 402. The offset between the high level of ST 402 and the high level of ST' 404 is determined by the diode connected PFET 416 or the diode connected NFET 418. The result of the offset is that the precharge transistor 35 is partly on during the evaluate phase so that it provides noise immunity and solves charge sharing problems; this is described in detail by Lee and Szeto. It will be appreciated that P-logic gates in the zipper logic system are controlled by a clock driver circuit which is complementary to clock driver circuit 31.
Even though zipper logic has improved noise immunity and has less problems from charge sharing, it does have several disadvantages. One disadvantage of the zipper logic approach is the use of two separate clock signals distributed to each logic gate, thereby consuming more semiconductor area.
Another disadvantage is that one of two problems arises depending on the choice of diode means 414. If diode-connected PFET 416 is used, subthreshold conduction through transistor 416 will cause the voltage level of the ST' 404 signal to continue rising to higher voltages, reducing the offset voltage until transistor 416 and the precharging transistor 35 (FIG. 3b) which is driven by signal 404 are eventually all completely turned off. This prevents making the zipper logic gate operate statically.
If diode-connected NFET 418 is used, the clock signal ST' 404 will not rise up to the intended offset voltage since body effect on transistor 418 raises its effective threshold voltage substantially (i.e., typically about one volt). In this condition, precharge transistor 35 of dynamic CMOS logic gate 30 (FIG. 3b) will be turned on substantially above the threshold conduction region, and will operate at a relatively high power consumption, negating the power advantage of dynamic CMOS logic gates. Differences in the body effect parameters and in the magnitude of the threshold voltages between diode-connected NFET 418 and precharge transistor 35 of dynamic CMOS logic gate 30 (FIG. 3b) make the relative power consumption and stability of the zipper dynamic gate 30 unpredictable.
From the foregoing discussion it can be seen that a need exists in the prior art for apparatuses and methods for allowing a dynamic CMOS logic gate to operate statically. This need requires that the statically operated dynamic CMOS logic gate consumes substantially less power and operates faster than a static CMOS logic gate and that the dynamic gate take less space on a semiconductor substrate than a static CMOS logic gate. This need also requires an apparatus and method for reliably providing static operation with controllable and minimized power consumption without the risk that true static operation, when the system clocks are stopped (e.g. held high), will result in logic/data errors. There is also a need in the prior art to provide statically operated dynamic CMOS logic gates which have improved immunity against noise and against charge sharing.